李華偉，女，漢族，畢業于中國科學院計算技術研究所，現任計算機體系結構國家重點實驗室研究員、博士生導師。2022年6月，李華偉任中國科學院計算技術研究所處理器芯片全國重點實驗室副主任、研究員。
人物經歷
教育經歷
工作經歷
2021年12月27日，李華偉當選為2021年度中國計算機學會會士。
2001年7月至今就職于中國科學院計算技術研究所，現為計算機體系結構國家重點實驗室研究員、博士生導師。
2016-01-01-至今，中國計算機學會容錯計算專委會，主任。
2016-01-01-至今，中國計算機學會，理事。
2014-12-31-2018-12-31,IEEE TVLSI期刊編委,Associate Editor。
2014-01-01-至今,《計算機研究與發展》編委。
2010-01-01-至今,《計算機輔助設計與圖形學學報》編委。
2009-08-2010-08月，美國UCSB大學電子與計算機工程系任訪問教授。
2007-12-30-2015-12-31,中國計算機學會容錯專業委員會，秘書長。
社會兼職
2019-10-16-今,中國計算機學會集成電路設計專業組,秘書長
2018-08-14-今,中國計量測試學會集成電路測試專業委員會,副主任兼秘書長
2016-12-31-2017-12-30,第十七屆全國容錯計算學術會議,大會主席
2016-01-01-2019-12-31,中國計算機學會容錯計算專業委員會,主任
2015-12-30-2019-12-31,中國計算機學會,理事
2014-01-01-今,《計算機研究與發展》,編委
2010-01-01-今,《計算機輔助設計與圖形學學報》,編委
2007-12-29-2015-12-30,中國計算機學會容錯計算專業委員會,秘書長
主要成就
科研成就
項目
主要從事VLSI測試、可靠設計、驗證、容錯計算領域的應用基礎研究工作。主持的主要國家項目如下：
1、國家自然科學基金重點項目，差錯容忍計算器件基礎理論與方法，2015/01-2019/12。
2、國家自然科學基金面上項目，考慮集成電路時延變異性的硅后定時驗證方法，2012/01-2015/12。
3、國家自然科學基金面上項目，避免過度測試的時延測試方法，2008/01-2010/12。
4、國家重點基礎研究發展計劃（973計劃）項目，高性能處理芯片的設計驗證與測試，2005/12–2010/12。
5、國家高技術研究發展計劃（863計劃）項目，可信計算平臺軟硬件系統安全測試評估模型、測試方法以及測試自動化技術，2007/07–2009/12。
6、國家自然科學基金面上項目，面向串擾的時延測試，2007/01-2009/12。
論文
Ying Wang, Yinhe Han, Cheng Wang, 華為 Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE Transaction on Computer Aided 設計 of Integrated Circuits and Systems (TCAD), Vol. 36, No.5, pp.705-718, 2017.
Jian Wang, 華為 Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Transaction on 計算機 Aided 設計 of Integrated Circuits and Systems (TCAD), Vol. 35, 二氧化氮, pp.285-297, 2016.
Yanhong Zhou, Tiancheng Wang, 華為 Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE Transaction on 計算機 Aided 設計 of Integrated Circuits and Systems (TCAD), Vol. 35, No.6, pp.999-1011, 2016.
Guihai Yan, Faqiang Sun, 華為 Li, Xiaowei Li, “CoreRank: Redeeming Imperfect 硅 by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors”, IEEE Transactions on Computers, Vol. 65, No.3, pp.716-729, 2016.
Yun Cheng, 華為 Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “Flip-flop Clustering based Trace Signal Selection for Post-硅 Debug,” Proc. of IEEE VLSI Test Symposium (VTS’17), Paper 3A-2, USA, April 2017.
Ying Wang, 華為 Li, Xiaowei Li, “Re-architecting the On-chip memory Sub-system of Machine-Learning Accelerator for Embedded Devices,” Prof. of IEEE International Conference On 計算機 Aided 設計, USA, Nov. 2016.
Ying Wang, Jie Xu, Yinhe Han, 華為 Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family”, IEEE/ACM Proceedings of 設計, Automation Conference (DAC), USA, 2016.
Ying Wang, Yinhe Han, Jun Zhou, 華為 Li, Xiaowei Li, “DISCO: A Low Overhead In-Network 數據 Compressor for 能量Efficient Chip Multi-Processors”, IEEE/ACM Proceedings of 設計, 自動化技術 Conference (DAC), USA, 2016.
Huina Chao, 華為 Li, Tiancheng Wang, Xiaowei Li and Bo Liu, “An accurate algorithm for computing mutation coverage in model checking,” Prof. IEEE International Test Conference, USA, Paper 16.2, Nov. 2016.
Yanhong Zhou, 華為 Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li, “Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage,”, Proc. of IEEE VLSI Test Symposium (VTS’16), Paper 1B-2, USA, April 2016.
Ying Wang, Yinhe Han, 華為 Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li, “PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3D Die-Stacked PCM”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.24, No.5, pp.1613-1625, 2016.
Ying Wang, Lei Zhang, Yinhe Han, 華為 Li, Xiaowei Li, “數據 Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.5, pp. 879-892, 2015.
Ying Wang, Lei Zhang, Yinhe Han, 華為 Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip 設計”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015.
Dawen Xu, Huawei Li, Amirali Ghofrani, KT Rolster Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014.
Binzhang Fu, Yinhe Han, 華為 Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant 路由 for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014.
Yuntan Fang, 華為 Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014.
Song Jin, Yinhe Han, 華為 Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833.
Ying Zhang, 華為 Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233.
Zijian He, Tao Lv, 華為 Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219.
Yuntan Fang, 華為 Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,” Proc. of IEEE VLSI Test Symposium (VTS’13), Paper 10B-3, Berkeley, CA, USA, May 2013.
Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, 二氧化氮, 2012, pp.236-247.
Songwei Pei, 華為 Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test 數據 Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169.
Songwei Pei, 華為 Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement 建筑,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577.
Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition 時間 Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800.
Minjin Zhang, 華為 Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982.
Songwei Pei, 華為 Li, and Xiaowei Li, “A Unified Test 建筑 for on-Line and Off-Line Delay Fault Detections", Proc. IEEE VLSI Test Symposium (VTS’11), 2011, pp.272-277.
[27]Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” Proc. 2011 International Symposium on VLSI 設計, Automation and Test (V LSI-DAT), invited paper in Special Session I (GPU Applications), Taiwan, April 2011.
華為 Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,”Proc. IEEE 41st International Test Conference (ITC’10), Paper 12.1, Austin, USA, Oct. 2010.
Zijian He, Tao Lv, 華為 Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations,” Proc. of IEEE 28th VLSI Test Symposium (VTS’10), Santa Cruz, USA, May 2010, pp.3-8.
Songwei Pei, 華為 Li, Xiaowei Li, “An On-Chip Clock Generation Scheme for Faster than-at-Speed Delay Testing”, Proc. of 設計 自動化技術 and Test in Europe (DATE’10), France, Mar. 2010, pp.1353-1356.
Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test Generation for Crosstalk-Induced Path Delay Faults,” 24th IEEE VLSI Test Symposium (VTS’06), Berkeley, CA, USA, May 2006.
華為 Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,”Journal of Electronic Testing: Theory and Applications, Vol. 21, 二氧化氮, 2005, pp.181-195.
[33]Huawei Li, Yue Zhang, and Xiaowei Li, “Delay Test Pattern Generation Considering Crosstalk-induced Effects,” IEEE 12th Asian Test Symposium (ATS’03), Xi’an, China, Nov. 2003, pp.178-183.
華為 Li, Zhongcheng Li, and Yinghua Min, “Reduction of Number of Paths to be tested in Delay Testing,”Journal of Electronic Testing: Theory and Applications, Vol.16, No.5, Oct. 2000, pp. 477-485.
研究領域
集成電路設計自動化、近似計算、容錯計算、設計驗證與測試。
主講課程
VLSI測試與可測試性設計
VLSI測試與可測性設計
數字電路的故障診斷與可靠設計
數字系統的故障診斷與容錯設計
參考資料：
獲得榮譽
人物評價
李華偉在微處理器全生命周期可靠設計和專用處理器自動設計的研究與應用方面取得了重要成績，CCF學術服務貢獻突出。（中國計算機學會夏培肅獎會士評選委員會評）
參考資料 >
李華偉.中國科學院大學.2024-08-15
【綜合新聞】祝賀計算所李華偉研究員當選CCF會士.中國科學院計算技術研究所.2024-08-14
李華偉個人主頁.中國科學院大學網站.2017-07-13